This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .
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LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The fault-tolerance is provided at design VHDL level, and does proceesor require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools.
LEON3 Processor – MechatronicsUSP
Your rating has been changed, thanks for rating! The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient SET errors in combinational logic. Retrieved from ” http: Archived copy as title Webarchive template wayback links Articles lacking reliable references from November All articles lacking reliable references Articles containing Spanish-language text Articles with Curlie links.
The certification was completed on May 1, This allows new users to quickly define a suitable custom configuration.
The LEON3 template designs can be configured using a graphical tool built on tkconfig leoj3 the linux kernel. The LEON3 processor has the following features:. LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications. Hardware iCE Stratix Virtex. Pfocessor is described in synthesizable VHDL. The LEON4 processor has the following features: To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed.
Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single event upset SEU errors in all on-chip RAM memories.
Free and open-source software portal. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.
LEON – Wikipedia
This section and the subsequent subsections focus on the LEON processors as soft IP cores peocessor summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution. This article is about the family of microprocessors. Views Read Edit View history.
Pre-synthesized FPGA programming files are also provided. For industrial and high-rel applications, ports for VxWorks 5. This page presents the major microprocessors used or to be used in most European space applications.
Only netlist distribution is possible. Archived from the original PDF on Flip-flops are protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity bits. Currently 5 out of 5 Stars. The LEON4 processor has the following features:.
LEON has a dual license model: Please improve this by adding secondary or tertiary sources. The NGMP has the following on-chip functions: Another objective was to be able to manufacture in a Single event upset SEU tolerant sensitive semiconductor process.
Airbus Defense and Space. Up to 16 CPU can be used in a multiprocessing configuration. It is highly configurable, and was designed for embedded applications with the following features on-chip:. A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration.